Keywords: Verilog | reg data type | wire data type | hardware description language | SystemVerilog
Abstract: This paper systematically examines the fundamental distinctions between reg and wire data types in Verilog and their application scenarios in hardware description languages. By analyzing the essential differences between continuous and procedural assignments, it explains why reg is not limited to register implementations while wire represents physical connections. The article uses examples such as D flip-flops to clarify proper usage of these data types in module declarations and instantiations, with a brief introduction to the rationale behind logic type in SystemVerilog.
Fundamental Concepts of Verilog Data Types
In the hardware description language Verilog, reg and wire are two fundamental data types whose design reflects different behavioral characteristics of digital circuits. Understanding their distinctions is crucial for writing synthesizable hardware description code.
The Nature of wire Data Type
The wire type represents physical connections used to link different components in a circuit. It lacks inherent storage capability and must be driven by either continuous assignment statements or module ports. When multiple drivers act on the same wire variable with conflicting values, an indeterminate state (X value) occurs. This characteristic accurately simulates signal contention in actual circuits.
The True Meaning of reg Data Type
Despite its name suggesting "register," the reg type does not necessarily correspond to physical registers. It represents data storage elements that retain their values until the next assignment within procedural blocks. The key distinction is that reg variables can only be assigned within procedural blocks (e.g., always, initial) and cannot be driven by continuous assignment statements.
Procedural vs. Continuous Assignments
Procedural assignment statements refer to assignments executed inside procedural blocks, where the target must be of reg type. For example, in a D flip-flop description:
module d_flip_flop(input clk, input d, output reg q);
always @(posedge clk) begin
q <= d; // Procedural assignment, q must be declared as reg
end
endmoduleContinuous assignment uses the assign keyword to drive wire type variables:
wire result;
assign result = a & b; // Continuous assignment, result must be wirePractical Considerations in Application
Within module declarations, output ports can be declared as reg type, but when the module is instantiated, its output ports must connect to wire type variables. This design ensures consistency in hierarchical design. reg can infer to either combinational or sequential logic, while wire typically corresponds only to combinational logic.
SystemVerilog Enhancement: The logic Type
SystemVerilog introduces the logic data type to eliminate confusion caused by the reg name. logic can be used in both continuous and procedural assignments but cannot have multiple drivers. When multiple assignments exist, it follows a "last assignment wins" principle, which doesn't fully align with hardware behavior but simplifies verification processes.
Synthesis and Implementation Considerations
During synthesis, reg variables may be implemented as flip-flops, latches, or pure combinational logic, depending on their usage context. Designers must select appropriate data types based on desired hardware behavior while considering consistency between simulation and synthesis.